Flash memory has become a research hot spot in non-volatile memories for its advantages of convenience, high storage density and good reliability. With developments of technology and storage requirements of electronic products, flash memory has been widely used in mobile and communication devices, such as mobile phones, laptop computers, PDAs and USB flash drives. Flash memory, as a kind of non-volatile memory, is operated by modifying the threshold voltage of the transistor or memory cell to control the on/off state of the channel, so as to realize the storage of data and ensures that the data stored in the memory will not be lost in case of power outage. Flash memory is also a special structure of electrically erasable programmable read-only memory. Currently, flash memory has occupied most of the market share of non-volatile semiconductor memories and has become a non-volatile semiconductor memory with the fastest developing speed.
However, when the existing flash memories are developing towards a higher storage density, it is difficult to increase the storage density by reducing the size of the device due to the restriction of the programming voltage. Moreover, further reducing the programming voltage of the device is facing great challenges due to the limitation of the structure. Generally, a flash memory is of a split gate type or a stacked gate type, or a combination thereof. Compared to a stacked-gate flash memory, a split-gate flash memory has unique advantages in programming and erasing operations for its special structure, therefore, it is widely used due to its high programming efficiency and its advantage of avoiding over-erase owing to its word line structure. However, the split-gate flash memory has one more word line than the stacked-gate flash memory, which makes chip area increase. To introduce memory cells with higher packaging density into a semiconductor memory device, the layout of memory device circuits with a smaller size must be used. Therefore, in order to solve the problems caused by high-density packaging of the memory cells, the structure of the semiconductor memory device must be improved.
So far, many attempts have been made to increase the density of memory cells. For example, EP0109853A2 disclosed an array of MOS transistors formed on a semiconductor substrate with a plurality of bit lines serving as the source and drain regions of the MOS transistors, wherein a plurality of conductive word lines are formed above the plurality of bit lines, being insulated from and perpendicular to the bit lines, each conductive word line serving as the gates of a plurality of MOS transistors. Each transistor of the memory array is formed in a region containing two bit lines and a single word line and forms a contact with each bit line. To avoid danger and reduce the capacitance between conductive lines, a thin film of field oxide is formed on bit lines to isolate the bit lines from the polysilicon lines. In addition, generally, between adjacent bit lines and adjacent polysilicon lines, a thick layer of field oxide is needed to isolate a memory cell from its adjacent cell, so as to minimize point coupling between them. As each bit line is connected to a conductive metal contact line, metal lines must be formed intensively on a single semiconductor wafer, and the increase of cell density will correspondingly increase the intensity of metal lines, as a result, the complexity and cost of the manufacturing process is largely increased because lines with very small critical dimensions need to be formed during the photolithography and etch processes. Therefore, such method for increasing density of memory cells has high requirements on process conditions and is not suitable for popularization and promotion.